muthike assignments: COMP 372 Assgn. # 5 Internal Circuit of 6810 Microprocessor

The MCM6810, a 128 x 8 chip designed by Motorola is used with its 6800 series processors. This means it stores 128 bytes at addresses from $00 to $7F. If you put any address on the 7 address pins, then the corresponding data appears on the 8 data pins. The time from a change of address to the appearance of the corresponding data is called the access time of the memory. Actually, it is the maximum access time, since each address has, in general, a different access time depending on where it is in the memory array. An access time of 450 ns was appropriate to processors with a 1 μs cycle time, assuming that the proper address would appear midway in the cycle, and the data would be read or written at the end of the cycle.

Since the data pins are connected to the processor's data bus, they must be put into a high-impedance state at all times except when the processor expects them to drive the bus during a read cycle. There are two control lines for the memory chip, the chip select (CS) and the read-write (RW) lines. When RW is high, data appears when CS is active. The 6810 has six CS pins, four active low and two active high. All must be active to say that CS is active.

When RW is low, CS has a different function. Instead of activating the data outputs, it strobes the data on the data bus into the current address on the trailing edge of its pulse. Different memory chips may work in different ways, but something like this occurs in any case. This happens to be the way the 6810 works.

When the 6810 is connected to the processor in the normal way, the RW line is connected to the R/W signal of the processor, which takes its proper value at the start of the cycle. CS is active during φ₂, which is the clock signal produced by the processor that is high during the last half of the bus cycle. If the 6810 were the only thing on the bus (and it will be for our initial test) one can simply use φ₂ as CS. In a more general case, CS will combine both φ₂ and an address decode depending on the current address output by the processor. Different devices on the bus will have different address decodes.